Публикация
R. Aliasgari Renani, V. Vasilevskiy, V. Vologin, R. Zaripov, O. Zinovchik, Y. Lvovich, and V. Chesnokov, ‘‘Investigation of FPGA resource utilization in manual and Simulink-generated Verilog implementations of image signal processing algorithms,’’ in Proc. DSPA Conference, 2026. Presentation